深圳安盛宇电子有限公司

STM8L051F3 is member of the STM8L ultra-low-power 8-bit family. STM8L051F3 features an enhanced STM8 CPU core providing increased processing power (up to 16 MIPS at 16 MHz) while maintaining the advantages of a CISC architecture with improved code density, a 24-bit linear addressing space and an optimized architecture for low-power operations.
The STM8L051F3 MCU includes an integrated debug module with a hardware interface (SWIM) which allows non-intrusive In-Application debugging and ultra-fast Flash programming. It features an embedded data EEPROM and low-power, low-voltage, single-supply program Flash memory.
The device incorporates an extensive range of enhanced I/Os and peripherals, a 12-bit ADC, a real-time clock, two 16-bit timers, one 8-bit timer, as well as standard communication interfaces such as an SPI, an I2C interface, and one USART.
The modular design of the peripheral set allows this device to have the same peripherals that can be found in different ST microcontroller families including 32-bit families. This makes any transition to a different family very easy, supported also by the use of a common set of development tools.
STM8L051F3 as all the value line STM8L ultra-low-power products are based on the same architecture with the same memory mapping and a coherent pinout.

All features
Operating conditions
Operating power supply: 1.8 V to 3.6 V Temperature range: −40 °C to 85 °C

Low-power features
5 low-power modes: Wait, Low-power run (5.1 μA), Low-power wait (3 μA), Active-halt with RTC (1.3 μA), Halt (350 nA)
Ultra-low leakage per I/O: 50 nA
Fast wakeup from Halt: 5 μs

Advanced STM8 core
Harvard architecture and 3-stage pipeline
Max freq: 16 MHz, 16 CISC MIPS peak
Up to 40 external interrupt sources

Reset and supply management
Low power, ultra-safe BOR reset with 5 selectable thresholds
Ultra-low power POR/PDR
Programmable voltage detector (PVD)

Clock management
32 kHz and 1 to 16 MHz crystal oscillators
Internal 16 MHz factory-trimmed RC
Internal 38 kHz low consumption RC
Clock security system

Low-power RTC
BCD calendar with alarm interrupt
Digital calibration with +/- 0.5 ppm accuracy
LSE security system
Auto-wakeup from Halt w/ periodic interrupt

Memories
8 Kbytes of Flash program memory and 256 bytes of data EEPROM with ECC
Flexible write and read protection modes
1 Kbyte of RAM
DMA
4 channels supporting ADC, SPI, I2C, USART, timers
1 channel for memory-to-memory

12-bit ADC up to 1 Msps/10 channels
Internal reference voltage

Timers
Two 16-bit timers with 2 channels (used as IC, OC, PWM), quadrature encoder
One 8-bit timer with 7-bit prescaler
2 watchdogs: 1 Window, 1 Independent
Beeper timer with 1, 2 or 4 kHz frequencies

Communication interfaces
Synchronous serial interface (SPI)
Fast I2C 400 kHz SMBus and PMBus
USART

Up to 18 I/Os, all mappable on interrupt vectors
Development support
Fast on-chip programming and non-intrusive debugging with SWIM
Bootloader using USART